The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with vertical gates.
Recently, a memory device with dimensions under 40 nm has been used to improve a degree of integration. However, it has been difficult to scale a transistor having a planar channel or a recess channel used in 8 F2 or 6 F2 cell architecture, where F is a minimum feature size, to have dimensions under 40 nm. Accordingly, a dynamic random access memory (DRAM) having 4 F2 cell architecture, which can improve the degree of integration to 1.5 to 2 times in the same scaling, is desirable and thus a semiconductor device with vertical gates is suggested.
The semiconductor device with vertical gates is fabricated by processing a substrate to have a pillar-type active pillar and a vertical gate surrounding the external walls of the active pillar. In the semiconductor device with vertical gates, a channel stretched in a vertical direction is formed on areas between the upper part and lower part of the active pillar.
In the fabrication of the semiconductor device with vertical gates, a buried bit line (BBL) is formed by performing an ion implantation process, and a trench process is performed to separate neighboring buried bit lines each other.
FIG. 1A is a cross-sectional view illustrating a semiconductor device with vertical gates according to the prior art. Hereinafter a method for forming the semiconductor device with vertical gates according to the prior art will be described.
Referring to FIG. 1A, an active pillar 12 having recessed sidewalls is formed by etching a substrate 11 using a protective layer 13 as an etch barrier, and the recessed sidewall of each active pillar 12 is surrounded by the gate insulation layer 17 and a vertical gate 14.
An impurity region is formed in the substrate 11 by the ion implantation process, and the impurity region is separated by forming a trench 16. In the trench formation process, the substrate 11 is etched to a depth which can divide the impurity region. The separated impurity regions become buried bit lines 15A and 15B.
As described above, the buried bit lines 15A and 15B are formed by performing the ion implantation process and the trench formation process. A photoresist mask is used in the trench formation process. The photoresist mask is called as a ‘BBL mask.’
FIG. 1B is a plan view illustrating a buried bit line according to the prior art. The buried bit lines 15A and 15B are separated each other by the trench 16.
Since etching process for separating the buried bit lines 15A and 15B is performed after the active pillar 12 is formed, it is comparatively easy to find a misalignment between the active pillar 12 and the trench 16.
FIG. 2A is a scanning electron microscopic view showing a BBL mask alignment; FIG. 2B is a scanning electron microscopic view showing a BBL mask misalignment; and FIG. 2C is a scanning electron microscopic view showing a damage of the protective layer due to the BBL mask misalignment.
If a misalignment occurs, the trench 16 is misaligned with the active pillar 12 as shown in FIG. 2B, or the protective layer 13 formed over the active pillar 12 is damaged and overlaid (see reference A) during an etching process for the trench formation as shown in FIG. 2C. Therefore, it is desirable for a new process to prevent the above overlay and align the trench and the active pillar.